As modern computer systems operate at increasingly higher speeds, the timing control signals communicated within the system must accordingly improve in accuracy. For many computer systems, particularly those which are microprocessor-based, the clock signal applied to the central processing unit, and other circuitry operating synchronously therewith, is preferably free from harmonic and other noise. Since signal noise is primarily due to parasitic inductance, the increase in signal switching speed required in high speed computers will also increase the amount of noise present on the signal. In addition, while propagation delays of the clock signal as it is communicated through buffers and other circuitry cannot be avoided, it is highly desirable that such delays be controllable and uniform.
Copending application Ser. No. 444,116, filed Nov. 30, 1989, assigned to Compaq Computer Corporation, and incorporated herein by this reference, describes a clock signal distribution scheme having reduced harmonic noise. In this scheme, the clock signal is distributed around the computer system as a sine wave rather than a square wave, so that over much of the length of the signal transmission paths in the system, the generation of harmonic noise is much reduced. At a location near a circuit which is controlled by the clock signal, such as a microprocessor, a clock squaring circuit is provided which receives the sine wave clock signal, and forms it into a square wave to which the clocked circuit can respond.
In a system constructed according to this arrangement, not only is the microprocessor controlled by the clock signal, but other circuits are also controlled by the same clock signal in order to operate synchronously therewith. Such other circuits may include memory controllers, co-processor circuits, and the like. As described in said application Ser. No. 444,116, a clock squaring circuit, or buffer, is thus provided physically near each circuit which is to be controlled by the same clock signal, with the sine wave clock signal communicated throughout the system to each of the circuits.
Particularly where such a system is to operate at increasingly higher speeds, the synchronization of the receipt of the clock signal by each clocked circuit becomes more critical. It has been observed that, for example in the arrangement described in said application Ser. No. 444,116, the propagation delays through individual clock squaring buffers vary, buffer to buffer, by on the order of 4 nsec. As is well known for integrated circuits generally, this variation in propagation delays is due to variables in the integrated circuit manufacturing process which affect parameters such as the gains, threshold voltages, and other transistor parameters, and also the values of impedances such as resistors and capacitors therein. Variation in the propagation delays may cause system inaccuracies or failures; in systems where the clock signal frequency is on the order of 33 to 66 MHz, small variations in propagation delays may be sufficient to cause such errors.
The variations in propagation delays may be reduced by measuring propagation delays of the individual buffer circuits, and matching buffers with similar propagation delays for use in the same computer system. Such matching is, at best, inconvenient in the manufacturing and maintenance of the computer systems.
It is therefore an object of this invention to provide a clock buffer circuit which allows for adjustment of the propagation delay therethrough.
It is a further object of this invention to provide such a circuit where the duty cycle of the buffer output remains fixed over the adjustment range of the propagation delay.
It is a further object of this invention to provide such a circuit which can receive a sine wave input and produce a square wave output.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following description together with the drawings.